In reply to sai_pra99:
Hi,
How do I verify an ALU in UVM?. In my SV test benches, I used to have mailbox drv2sb and mon2sb to check my transactions and expected output pass & fail. And when it comes to UVM
1)Should I use predictor and comparator to verify? If yes, should I have an analysis port for the driver in which I predict the output and send them to my scoreboard and then compare it with that of received monitor outputs in the scoreboard? Will this be a good solution? .Should I be implementing this by using uvm_tlm_analysis_fifo?
2)Any other solution to verify it?
Generate automatically a UVM environment using a UVM Framework Generator like the one from Doulos (https://www.doulos.com/knowhow/sysverilog/uvm/).
Then add ascorboard and a functional coverage collector.