In reply to ben@SystemVerilog.us:
Ben , I was actually looking for a ( crude ) solution without any operator ( within , intersect etc. )
I ended up coding the following :: EDA_throughout_ALT
For stimulus via +define+M2 I observe the same O/P as the original code ( using throughout )
However for +define+M1 due to Vacuous pass there is No assertion Failure at TIME : 70 .
I tried using strong operator in consequent of property ’ ab ’ but it throws Compilation Error .
**
Any suggestion on how Vacuous Pass of antecedent in property ’ checkMode ’ could
make the assertion FAIL ?**