Add queue inside flip flop

SystemVerilog
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3

In reply to dave_59:

Thanks to your reply.

As I said I am new to systemverilog and fpga. It seems that many features of systemverilog (verification) are not synthesized into fpga. (failure when compiling the design).

I am using altera quartus II 16.1. Here is a list of compilation failures I found :

  1. stream operator
shortint msg_size;
{>>msg_size} = {<<8{in_data[pos-:16]}};

How to get first 16 bits data from in_data as shortint in a synthesizable way?

  1. dynamic array
typedef struct {
  byte no_entries;
  int data[];
} mystruct;
function automatic mystruct get_mystruct(ref logic[4095:0] in_data, input int pos) ;
  static mystruct;
  mystruct.no_entries = get_short(in_data, pos);
  mystruct.data = new[mystruct.no_entries]; // set array size at runtime, it is not supported
  for (int i = 0 ; i < mystruct.no_entries ; i++) begin
    mystruct.data[i] = get_int(int_data, pos);
  end
  return mystruct
endfunction

How to create a synthesizable dynamic array? any workaround?

  1. queue
mystruct mystruct_var[$]; // not support in qurtus II

any generic queue module example?