I tried it with some seeds and it seems to work. Please give it a try.
``` verilog
module d2_arr_unique;
parameter N = 8 ;
class A;
rand bit arr [N][N];
// Absolute value
function int abs(int val);
return val >=0 ? val : -(val);
endfunction
// column sum == 1
constraint col
{
foreach (arr[r1,c1]) foreach(arr[r2,c2])
{
(c1 == c2) && (r1 != r2) && arr[r1][c1]==1 -> arr[r2][c2]==0;
}
}
// row sum == 1
constraint row
{
foreach(arr[i]) {arr[i].sum(item) with (int'(item))==1;}
}
// Take care that diagonals are zero
constraint diag
{
foreach (arr[r1,c1]) foreach (arr[r2,c2])
{
(abs(r1-r2) == abs(c2-c1)) && r1!=r2 && c1!=c2 && arr[r1][c1]==1 -> arr[r2][c2]==0;
}
}
// Print array
function void print_arr();
for(int i=0; i<N; i++) begin
for (int j=0; j<N; j++) begin
$write("[%0d]",arr[i][j]);
end
$display("\n");
end
endfunction
endclass
A a= new;
initial begin
void'(a.randomize());
a.print_arr();
$finish();
end
endmodule