Achieving Unique Columns

SystemVerilog
,
4

works for column now I am working on diag


``` verilog

rand bit arr [N][N];

		constraint col
		{
			foreach (arr[r1,c1]) foreach(arr[r2,c2])
				{
					c1 == c2 && r1 != r2 && arr[r1][c1]==1 -> arr[r2][c2]==0;
				}
		}
		
		

		constraint sum
		{
			foreach(arr[i]) {arr[i].sum(item) with (int'(item))==1;}
		}