Achieving Unique Columns

SystemVerilog
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2

In reply to Etrx91:

Use a nested foreach:

   constraint c {
      foreach (arr[r1,c1]) foreach(arr[r2,c2]) {
          c1 == c2 && r1 != r2 -> arr[r1][c1] != arr[r2][c2]; // unique col
          r1 == r2 && c1 != c2 -> arr[r1][c1] != arr[r2][c2]; // unique row
   }}