Accessing a generate block hierarchy

SystemVerilog
2

In order to reference an instance created inside a generate-for loop, you must use a constant or another genvar variable. That is because GENERATE_HEADER is not an array, it is part of a hierarchical scope name. So you could do

virtual some_interface some_interface_arr[0:2];
generate 
for (i=0;i<3;i++)
initial some_interface_arr[i]=testbench.GENERATE_HEADER[i].some_interface_inst;
end
endgenerate

If you are using UVM/OVM you should be setting these interfaces in the config_db directly instead of assigning them to a local virtual interface array.