Access Rights in Ral

UVM
6

In reply to Anudeep J:

You are right, there is a priority. If you set the access policy for the field then the access right from the reg does not overwrite the field feature. See the following example code:

class cmd_reg extends uvm_reg;
`uvm_object_utils(cmd_reg)

    uvm_reg_field TX_READY;             // RO - so not rand

rand uvm_reg_field TX_DMA_RUN; // RW

function new(string name = “cmd_reg”);
super.new(name, 16, UVM_NO_COVERAGE );
endfunction : new

virtual function void build();

  this.TX_READY   = uvm_reg_field::type_id::create("TX_READY");
  this.TX_DMA_RUN = uvm_reg_field::type_id::create("TX_DMA_RUN");
  
  this.TX_READY.configure(this, 1, 15, "RO", 0, 1'h0, 1, 0, 0);
  this.TX_DMA_RUN.configure(this, 1, 14, "RW", 0, 1'h0, 1, 1, 1);

endfunction : build

endclass : cmd_reg

Field TX_READY is configured for “RO”
Field TX_DMA_RUN is configured for “RW”.

class regmodel extends uvm_reg_block;
`uvm_object_utils(regmodel)

cmd_reg cmd;
…
this.default_map.add_reg(cmd, .offset(0), .rights(“RW”));
…
endclass

Does not change the access policy of the reg fields.