First, SystemVerilog does not support method overloading.
Huh? Derived classes can overload methods of the parent class.
To be fair - I don’t know C++, and I may have the terminology wrong…
Your particular example implies an implicit cast from base_ic to foo_c. You’d need a dynamically typed language to do that.
foo_c is an implementation of base_ic. The standard indicates this is ok with virtual methods and abstract classes, but isn’t clear in the case of interface class. I don’t think it’s strictly a derived class, hence the error - but would certainly be much more convenient it it worked.
Regards,
Mark