Hi guys:
I have a interface usage scenario,
interface a0 will declare a variable “data”,
interface a1 declare sub-field “data_a”, “data_b”。
signal “data” is concatenated from “data_a” and “data_b”.
Is the code below right ? or is there any way to archive this purpose?
interface a0();
bit is_master;
logic [31:0] data;
//...
endinterface
interface a1();
a0 a();
logic [15:0] data_a;
logic [15:0 data_b;
initial begin
#0;
if (a.is_master) begin
force a.data = {data_a, data_b};
end
else begin
force {data_a, data_b} = a.data;
end
end
endinterface