A way to write constraint which allocates active channels to ports

SystemVerilog
,
6

In reply to Michael54:

you can control complete i/o mapping using below code:



class dut_io_map #(N_OUTPUT=2, N_INPUT=16);
  rand int unsigned io_map[N_INPUT][N_OUTPUT];
  rand bit use_iport[N_INPUT];
  rand bit use_oport[N_OUTPUT];
  rand int use_n_iport;
  rand int use_n_oport;

  constraint map_c {
     use_n_iport                      inside {[1:N_INPUT]};
     use_iport.sum() with(int'(item)) == use_n_iport;
     use_oport.sum() with(int'(item)) inside {[1:3]};
     
     foreach(io_map[i,j])  { io_map[i][j] inside {0,1}; }
     foreach(use_iport[i]) { 
                              io_map[i].sum() == use_iport[i]; 
                             (use_oport[0]==0) -> (io_map[i][0] == 0);
                             (use_oport[1]==0) -> (io_map[i][1] == 0);
                           }
   }

   function void post_randomize();
     $display("active out_port : port_0=%b, port_1=%b", use_oport[0], use_oport[1]);
     $display("active in_port  : %p, num in ports=%0d", use_iport, use_n_iport);
     foreach(io_map[i]) begin
       $display("input_port_%02d=%b : io_map=%p",i,use_iport[i],io_map[i]);
     end
   endfunction

endclass

module test;
  dut_io_map txn=new();

  initial begin
     txn.randomize() with {
        //use_oport[0]==1; 
        //use_oport[1]==0;
        use_n_iport ==7;   //Num of Active input ports
        io_map[2][1]==1;   //input 2 mapped to output 1
        io_map[5][0]==1;   //input 5 mapped to output 0
        use_iport[9]==1;   //input port 9, random out port mapping
        };
  end

endmodule


/*
OUTPUT:
active out_port : port_0=1, port_1=1
active in_port  : '{'h0, 'h0, 'h1, 'h1, 'h0, 'h1, 'h1, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h0, 'h0, 'h0} , num in ports=7
input_port_00=0 : io_map='{'h0, 'h0} 
input_port_01=0 : io_map='{'h0, 'h0} 
input_port_02=1 : io_map='{'h0, 'h1} //
input_port_03=1 : io_map='{'h1, 'h0} 
input_port_04=0 : io_map='{'h0, 'h0} 
input_port_05=1 : io_map='{'h1, 'h0} //
input_port_06=1 : io_map='{'h0, 'h1} 
input_port_07=1 : io_map='{'h0, 'h1} 
input_port_08=0 : io_map='{'h0, 'h0} 
input_port_09=1 : io_map='{'h1, 'h0} //
input_port_10=0 : io_map='{'h0, 'h0} 
input_port_11=1 : io_map='{'h1, 'h0} 
input_port_12=0 : io_map='{'h0, 'h0} 
input_port_13=0 : io_map='{'h0, 'h0} 
input_port_14=0 : io_map='{'h0, 'h0} 
input_port_15=0 : io_map='{'h0, 'h0} 
*/