A simple assertion; req implies ack; does not fail

SystemVerilog
, , ,
4

In reply to ben@SystemVerilog.us:

Ben, Thanks for the solution.

So, I also tried removing ‘until’ and still the test did not fail.

I tried

$rose(req) |=> !req[*1:10] ##1 ack ##1 !ack;

Here, the testbench is the same. ack stays high for more than one clock (when it should de-assert after 1 clock) and the test does not fail.

I understand ‘until’ is probably not the best choice but could you please explain why it does not work? It completely negates my understanding of ‘until’

Appreciate any further insight you can share.

Thanks.