In reply to ben@SystemVerilog.us:
SystemVerilog is statically typed meaning the compiler must determine all expression type at compile/elaboration. The width of a variable/operand is part of the type. An operand can be buried deep inside the context of an expression. The compiler has to determine the widths of all operands and propagate them through the entire expression through a complex set of rules. Doing this at runtime would have a significant impact on performance.
There is a simpler way of creating the mask in a single expression.
let range(val, width) = ( val & (2<<width)-1 )
if ( range(v,k) ) > 3)