Xor() array reduction method

SystemVerilog
, ,
1

Hi,

I have the following code inside a task:



logic in_act       = 0;
logic in_reg [$:5] = '{0,0,0,0,0,0};

// ...

in_act = in_reg.xor() with (item.index < 4);
$display("in_reg is           : %p",in_reg);
$display("in_act from xor()   : %0b",in_act);
$display("in_act from in_reg ^: %0b",in_reg[3] ^ in_reg[2] ^ in_reg[1] ^ in_reg[0]);

Simulator output:

in_reg is : '{1, 0, 1, 1, 1, 1}

in_act from xor() : 0

in_act from in_reg ^: 1

The “in_reg” queue is modified on every positive edge of a clock, the
two left most bits are deleted and two new bits (interface signals) are pushed
to the tail of the queue (push_back(…);), i.e. the queue is used as a
shift register.
Now after this operation I need the xor() value of the four leftmost bits.
As you can see the result is different. The array reduction method never results
in a “1”, why?

EDIT #1:

The xor() reduction method on the whole queue works as intended.

2

In reply to Fipser@VA:

I believe you want to write

in_act = in_reg.xor() with (item.index < 4 ? item  : 0 );
3

In reply to dave_59:

In reply to Fipser@VA:
I believe you want to write

in_act = in_reg.xor() with (item.index < 4 ? item  : 0 );

Does this iterate through all items, checking wether the item index is < 4 and if not, xor’ing the remaining items with 0?

4

In reply to Fipser@VA:

Correct.

5

In reply to dave_59:

Thanks! So you always have to keep in mind that the reduction methods consider all items and you have to decide what to do with the remaining items, the ones not matching the condition.