so a bit changes every cycle. So we need to check if by the end of 32 cycles, we have 16 changed bits.
In reply to pghosh:
Again, there is no question here. Just an assignment. But I do have a number of questions for you.
Does at least bit have to change a every cycle, or do you only care about the difference between the start and ending values?
Is there a specific start and end to the sequence, or this a continuous stream of overlapping sequence of values?
In reply to dave_59:
This is a challanging assertion. The following does work. Below is the testbench and results.
// A bit in a 32 bit number changes every cycle and
// at the end of 32 cycles 16 OF THE 32 bits changed?
property p_32;
bit[31:0] v_past, v_xor, vcount, v_or;
($rose(a), v_past=v, v_or=0) |=>
($countones(v ^ v_past==1) ##0 // 1-bit change
(1, v_or = (v_or | v_past^v)) // track bit that changed
##0 (1, $display("%t $countones(v_or) %d", $realtime, $countones(v_or))) // debug
) [*32] ## 0 $countones(v_or)==16 ;
endproperty
// a bit in a 32 bit number changes every cycle and at the end of 32 cycles
// if you have 16 bits changed?
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
timeunit 1ns; timeprecision 100ps;
bit clk, a, b;
bit[31:0] v;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
/* property p_change32; // DOES NOT DO WHAT INTENDED
bit[31:0] v_past, v_xor;
($rose(a), v_past=v) |=> ((1, v_xor=v_past^v) ##0
$countones(v_xor)==1 ##0 (1, v_past=v)) [*32];
endproperty
ap_change32: assert property(@ (posedge clk) p_change32); */
//;
property p_32;
bit[31:0] v_past, v_xor, vcount, v_or;
($rose(a), v_past=v, v_or=0) |=>
($countones(v ^ v_past==1) ##0 // 1-bit change
(1, v_or = (v_or | v_past^v)) // track bit that changed
##0 (1, $display("%t $countones(v_or) %d", $realtime, $countones(v_or))) // debug
) [*32] ## 0 $countones(v_or)==16 ;
endproperty
ap_32: assert property(@ (posedge clk) p_32);
initial begin
bit va;
bit[31:0] vb, vpast;
repeat(200) begin
@(posedge clk);
if (!randomize(va, vb) with
{ va dist {1'b1:=1, 1'b0:=0}; // vb != $past(vb); $countones(vb)==1;
$countones(vb ^ vpast)==1;
}) `uvm_error("MYERR", "This is a randomize error")
vpast=vb;
a <= va;
v <= vb;
end
$stop;
end
endmodule
# 500 $countones(v_or) 1
# 700 $countones(v_or) 2
# 900 $countones(v_or) 3
# 1100 $countones(v_or) 4
# 1300 $countones(v_or) 5
# 1500 $countones(v_or) 6
# 1700 $countones(v_or) 6
# 1900 $countones(v_or) 7
# 2100 $countones(v_or) 8
# 2300 $countones(v_or) 9
# 2500 $countones(v_or) 9
# 2700 $countones(v_or) 9
# 2900 $countones(v_or) 10
# 3100 $countones(v_or) 10
# 3300 $countones(v_or) 10
# 3500 $countones(v_or) 10
# 3700 $countones(v_or) 10
# 3900 $countones(v_or) 11
# 4100 $countones(v_or) 11
# 4300 $countones(v_or) 12
# 4500 $countones(v_or) 13
# 4700 $countones(v_or) 14
# 4900 $countones(v_or) 14
# 5100 $countones(v_or) 14
# 5300 $countones(v_or) 14
# 5500 $countones(v_or) 14
# 5700 $countones(v_or) 15
# 5900 $countones(v_or) 16
# 6100 $countones(v_or) 17
# 6300 $countones(v_or) 17
# 6500 $countones(v_or) 17
# ** Error: Assertion error.
For something more complicated, consider using tasks, as explained in my paper.
2. SVA Alternative for Complex Assertions Concurrent SVA is a powerful assertion language that expresses the definition of properties in a concise set of notations and rules; its use is very wide spread and is definitely encouraged. However, SVA is designed for a static world andis sometimes diffuclt to express when the problems are comples. This included paper then provides examples that demonstrate how some of those the SVA limitations can be overcome with the use of tasks, but yet maintain the spirit (but not vendor’s implementations) of SVA. The paper was published at Verification Horizons - March 2018 Issue | Verification Academy
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- Verification Horizons - March 2018 Issue | Verification Academy
- SVA: Package for dynamic and range delays and repeats | Verification Academy
- SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
FREE BOOK: Component Design by Example
… A Step-by-Step Process Using VHDL with UART as Vehicle
http://systemverilog.us/cmpts_free.pdf
In reply to dave_59:
This was an interview question. And I had come up with a solution but wasn’t sure if it was right. Hence, I posted the question on the forum.
There is no such constraint like a bit has to change every cycle, there might be some cycles when there is no bit change.
There is no start or end to the sequence, we have to check the # of changed bits at the end of 32 cycles.
In reply to ben@SystemVerilog.us:
Thank you, Ben.
I had a similar approach. If you can check this once, it would be great.
sol:
property p;
bit[31:0] v;
bit flag;
($countones($past(a,1)^a),v=0) |-> ((1, v=v+1)[*32] |=> (v==16|->flag==1);
endproperty
assert property(@(posedge clk)p);
Thanks again.
In reply to pghosh:
In reply to ben@SystemVerilog.us:
This is a very hard interview question. when you say There is no start or end to the sequence, we have to check the # of changed bits at the end of 32 cycles that means that for every 32 cycles you have 16 changes. Kind of unusual for a requirement. Maybe they were looking at your approach. On
There is no start or end to the sequence, we have to check the # of changed bits at the end of 32 cycles
property p;
bit[31:0] v;
bit flag;
($countones($past(a,1)^a),v=0) |-> ((1, v=v+1)[*32] |=> (v==16|->flag==1);
endproperty
assert property(@(posedge clk)p);
It is incorrect, and does not say anthing. In fact, it is always vacuous.
- ($countones($past(a,1)^a),v=0) // says if there is a change
- |-> ((1, v=v+1)[*32] // at the end of 32 cycles, v==31, or true for an antecedent
- |=> (v==16|->flag==1); // since v==31, v–16 is false, thus vacuity
You have way too many implication operators. Actualy, your response. sorry to tell you that, shows me as an interviewer that you really do not understand SVA.
My preferred solution is to use a task as explained in my paper
he paper was published at https://verificationacademy.com/news/verification-horizons-march-2018-issue
If you want to do homework, write the detailed requirements in English, then write it as a task per my model in that paper, and then come back to this forum; we’ll critique it.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- https://verificationacademy.com/news/verification-horizons-march-2018-issue
- SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
- SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
In reply to ben@SystemVerilog.us:
Thank you for your help, Ben.
I was unaware of the correct use of the comma operator for assigning a local variable. Your explanation of my code in pieces helped me understand that.
I will definitely go through the paper you have mentioned to have a better understanding.
In reply to pghosh:
BTW I wanted you to go through paper so that you can understand the conceptual model behind SVA. For those who want an SVA solution, I commented out a few lines of my
Original code.
property p_32;
bit[31:0] v_past, v_xor, vcount, v_or;
//($rose(a), v_past=v, v_or=0) |=>
// ($countones(v ^ v_past==1) ##0 // 1-bit change
( (1, v_or = (v_or | v_past^v)) // track bit that changed
// ##0 (1, $display("%t $countones(v_or) %d", $realtime, $countones(v_or))) // debug
) [*32] ## 0 $countones(v_or)==16 ;
endproperty
ap_32: assert property(@ (posedge clk) p_32);
BTW, consider reading a good book on SVA, I know of one good book :)
Ben systemverilog.us