Wildcard bin for Transition and Value Range

SystemVerilog
,
1

Hi ,

I was covering the following transitions and value range via wildcard bins ::


   bit [3:0]  data ;

   covergroup DATA ;  
   
       wild: coverpoint ( data ) 
      {   
     wildcard bins  trans[] = ( [ 4'b000? : 4'b001? ] =>  [ 4'b110? : 4'b111? ]  )  ;  //  Legal ?  
     wildcard bins  val[]   = { [ 4'b000? : 4'b001? ] } ;           //  Legal ?   
      }                                                                                      
   endgroup

My expectation was I would observe 4 dynamic bins for val and 16 dynamic bins for trans ..

However I observe Error with the above syntax as ? is being treated as 4-state value ( although data is bit type ).

I know LRM restricts usage of X / Z as range but since I have 2-state type , what does the LRM say about above scenario ?

2

In reply to hisingh:
LRM restricts usage of X / Z as range.

3

In reply to dave_59:

Yes , I do agree on that ( LINK :: using-4-state-variable-coverpoint )

But since the covergroup expression is bit type i.e 2-state , shouldn’t the above code translate to ::


wildcard bins  trans[] = ( [ 4'd0 : 4'd3 ] =>  [ 4'd12 : 4'd15 ] )  ; //  16  Dynamic  bins
wildcard bins  val[]   = { [ 4'd0 : 4'd3 ] } ;                        //   4  Dynamic  bins

I understand that generally we don’t discuss tool related issues , but some tools generate bins as per above logic .

My intention however is to understand from LRM’s perspective .


LRM  19.5.4  states  :: 

" A wildcard bin definition causes all X, Z, or ? to be treated as wildcards for 0 or 1. "

" A wildcard bin definition only considers 2-state values; sampled values containing X or Z are excluded "

Shouldn’t the ? translate to 1’b0 or 1’b1 ? ( as there are no X / Z bits sampled )