why we always declared clock in top module? can any one tell me the reason
In reply to lalithjithan:
why we always declared clock in top module? can any one tell me the reason
Clocking in a chip is an art on its own. It a typical FPGA or ASIC design, the clock is generated from an oscillator crystal and connected to the chip. I believe that there may be chips that allow the crystal to be connected to the chip. In any event, once inside the chip, the clock goes through an internal network of clock distribution so as to ensure that all FFs are clocked at the same time with minimum skew between them.
Now, back to your question “why we always declared clock in top module?”
- To emulate the external nature of the clock in relation to subpartitions
- To emulate, if needed, the connection of different buffered clocks to the various partitions.
- To emulate, if needed, clock jitters of variations to the various partitions.
- To allow gate-level/RTL level mix in a simulation.
Ben Cohen
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