why there is a delay of one clock cycle while using clocking block?
In reply to shubham dubey:
why there is a delay of one clock cycle while using clocking block?
There is no delay. You need to present sample code on how you use the clocking block.
Did you read 1800’2012 14.3 Clocking block declaration?
clocking bus @(posedge clock1);
default input #10ns output #2ns;
input data, ready, enable = top.mem1.enable;
output negedge ack;
input #1step addr;
endclocking
In the preceding example, the first line declares a clocking block called bus that is to be clocked on the positive edge of the signal clock1. The second line specifies that by default all signals in the clocking block shall use a 10ns input skew and a 2ns output skew. The next line adds three input signals to the clocking block: data, ready, and enable; the last signal refers to the hierarchical signal top.mem1.enable. The fourth line adds the signal ack to the clocking block and overrides the default output skew so that ack is driven on the negative edge of the clock. The last line adds the signal addr and overrides the default input skew so that addr is sampled one step before the positive edge of the clock.
Unless otherwise specified, the default input skew is 1step and the default output skew is 0. A step is a special time unit whose value is defined in 3.14.3. A 1step input skew allows input signals to sample their steady-state values in the time step immediately before the clock event (i.e., in the preceding Postponed
region).
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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In reply to ben@SystemVerilog.us:
But in 1800’2012 14.4 it has been written that
“output (or inout) signals are driven skew simulation time units after the corresponding clock event”
what’s this means?
Isn’t this is what happens with flip-flops? After the clock, the output may change after a delay, also known as “hold time”.
Ben Ben@systemverilog.us