Why is the base class constraint not overriding the parent class constraint?

SystemVerilog
, , ,
1

Hello! I’m trying to override the parent class constraint by declaring a child class constraint. Rather than overriding, it is just taking the child class constraint as a conflict and data and addr that are associated with pkt2 are being attributed to 0. Why?

class packet1;
	randc bit [4:0]addr;
	randc bit [7:0]data;
	
constraint C1{addr<25;data<30;}

	function print();
		$display("\n addr=%0d,data=%0d",addr,data);
	endfunction

endclass:packet1


class packet2 extends packet1;
	
constraint C2{addr!=0;data>35;}
	
		packet1 p1;
	
	function print1();
		$display("\n addr=%0d,\t data=%0d",addr,data);
	endfunction
	
endclass:packet2

module constraint_ex1;
	packet1 pkt1;
	packet2 pkt2;
	
	initial begin
		pkt1 = new();
	
		$display("\n----------------\t PACKET_1 DATA\t------------------------------------------");
			repeat(5)
				 begin
					pkt1.randomize;
					pkt1.print();
				end 
		$display("\n----------------\t PACKET2 DATA\t------------------------------------------");
				pkt2 = new(); repeat(5)
				begin
					pkt2.randomize;
					pkt2.print1();
					//$display("addr=%0d,data=%0d",pkt2.addr,pkt2.data);
				end
		$display("----------------------------------------------------------------");
		end
endmodule
2

In reply to Shashank Gurijala:

Constraint name in child class should be same as constraint name in parent class to override the constraint.


class packet1;

     constraint C1{addr<25;data<30;}
      ///other code ...

endclass:packet1

class packet2 extends packet1;
 
     constraint C1{addr!=0;data>35;}   // constraint name should be same if want to override 

///other code ...

endclass : packet2

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