What does this get synthesized to?

SystemVerilog
1 
always @*
begin
    if(a) begin
         case(b)
           1`b0:y=y+1;
           1`b1:y=c;
         endcase
    end
end

It was one of the Interview questions

2

In reply to Mithil Amaranath:

Time to do your homework:
https://www.amazon.com/RTL-Modeling-SystemVerilog-Simulation-Synthesis/dp/1546776346