I have a peripheral-based design with several components that need to be initialized at the beginning. This 6ms of sim time is eating my lunch; the initialization works perfectly, it never changes, yet I’ve got to sit and wait every single sim run for the components to boot up. This is a huge waste during debug.
Curious if anyone has encountered a problem like this. I’d basically like the sim to “skip” all this time at bootup.
Otherwise, I’ve got to jerry-rig all the components to have their init data at powerup, perhaps do a “force” on my FSM to to jump it ahead to the area of interest.
thoughts?
Your simulator probably has checkpoint and restore capabilities. You run the simulation to a specific point and save the state. After that you can restore the state and pick up after initialization.
If your RTL and testbench code is all VHDL / Verilog / SystemVerilog then its pretty straightforward. If you’ve got SystemC as well then it can get a little dicey; it depends on the simulator.
So far, it appears the tool (rivierapro) datasets are intended to be a historical record of the sim, and not a system state that can be plugged back into the system, and continued off from.
This is evident in that the sim command creates a blank dataset everytime, with no option to use an existing set.
I’ll ping aldec about it. if anyone has any further suggestions, help me out.
In reply to bmorris:
One of the Forum Reminders is
**Do NOT ask tool questions. Contact your tool vendor directly for support!
**
We want to stay vendor-neutral in this forum, thus we should not name a particular vendor, nor should we address any vendor’s strengths or weaknesses. This forum is focussed on language uses and issues, definitely not tools. We can talk about tools in general, like Your simulator probably has checkpoint and restore capabilities.
I suggest that you edit your post by removing ALL references to particular vendors.
Ben SystemVerilog.us