http://www.deepchip.com/items/0534-05.html is a very interesting users feedback on the subject.
I fully agree with the following 2 comments because assertions, the bases for inputs to formal, clarify the requirements :
If I had to go and construct a team to build the chip right now, I would actually completely rearrange how the whole build would be. It would start with designing using formal. Adoption for formal is a lot more powerful if you come at it from a design background."
…
“It would be good to have “formal friendly” design specification, as sometimes the bugs are results of interaction of 7 or 8 designers. People sometimes have misunderstandings of what a specific paragraph in a document means.”
Ben Cohen http://www.systemverilog.us/
- SystemVerilog Assertions Handbook, 3rd Edition, 2013
- A Pragmatic Approach to VMM Adoption
- Using PSL/SUGAR … 2nd Edition
- Real Chip Design and Verification
- Cmpt Design by Example
- VHDL books