Variable use in part-select

SystemVerilog
1

Hi,

In the code shown below how could I achieve the bit slicing [without running constant variable error for part-select] assuming that bit_width will change based on certain conditions in my code.



module tb;
  
  bit [31: 0] adc_in;
  int adc_i_data [8] = '{3, 3, 3, 3, 3, 3, 3, 3};
  int adc_q_data [8] = '{3, 3, 3, 3, 3, 3, 3, 3};
  bit [3: 0] adc_cnt = 4'h8;
  int bit_width = 1;
  
  initial
     begin
       for( int i = adc_cnt-1; i >= 0; i--)
         adc_in |= ({adc_i_data[i][bit_width : 0],adc_q_data[i][bit_width : 0]} << i*bit_width*2) ;
     end

     
endmodule : tb
2

In reply to nnd:

You cannot have variable width slices in SystemVerilog. You need to use a mask.

module tb;
  bit [31: 0] adc_in, mask
  int adc_i_data [8] = '{3, 3, 3, 3, 3, 3, 3, 3};
  int adc_q_data [8] = '{3, 3, 3, 3, 3, 3, 3, 3};
  bit [3: 0] adc_cnt = 4'h8;
  int bit_width = 1;
 
  initial
     begin
       mask = (33'b1 << bit_width) - 1; //33'b1 needed when bit_width = 32
       for( int i = adc_cnt-1; i >= 0; i--) begin
         adc_in |= (adc_q_data[i] & mask) << bit_width*2*i) ;
         adc_in |= (adc_i_data[i] & mask) << bit_width*(2*i+1)) ;
       end 
     end
endmodule : tb