Variable in BIN Name in System Verilog

SystemVerilog
,
1

Hi,

Is it possible to have a bin of 2D array. For example, I have 16 slots and each slot can have 4 value. I need to check if all 4 values for each slot is covered or not i.e need 64 bins.


bit [3:0] i;

covergroup cg(ref bit [3:0] i) @ (sample_event)
    coverpoint slot[i]{
       bins val[i][] = {[0:$]} ;
  }
endgroup

cg slot_cg;
initial begin
for(i=0;i<15;i++)
  slot_cg = new(i);
end

This is a syntax error though. Could you help me understand why and is there something I can do on the same lines??

2

In reply to Dilsya:

You want an array of covergroups

bit [1:0] slots[16];
covergroup cg(ref bit [1:0] slot) @ (sample_event)
   option.per_instance=1;
   coverpoint slot {
       bins val[] = {[0:$]} ;
   }
endgroup

cg slot_cg[16];
initial begin
   foreach(slots_cg[si]) slot_cg[si] = new(slots[si]);
end