The 'var' keyword is missing

SystemVerilog
1

Hi All,

I got error, "The ‘var’ keyword is missing. Not sure what is wrong with below code. Any suggestion ?
pkgs/nvx_aes_shr_ram_c.sv(15): (vlog-2294) The ‘var’ keyword is missing.

typedef struct packed {
logic [ 255:0] key1; // AES KEY
logic [ 255:0] key2; // XTS KEY
logic [ LBAW-1:0] lba; // Logic Block Address
logic [ 63:0] bcnt; // Block Count
logic [ 127:0] iv; // Initial Vector
logic [NSIDW-1:0] nsid; // Name Space ID
logic val; // Valid
logic byp; // Bypass
logic ren; // Key could be used during read (decrypt == 1)
logic wen; // Key could be used during write (decrypt == 0)
logic [ 1:0] ksize;// Key Size: 0: 128; 1: 256; 2: 192 (not supported in NVME MAES)
} shr_entry_s;

class nvx_aes_shr_ram_c extends uvm_object;
/** UVM Object Utility macro */
`uvm_object_utils(nvx_aes_shr_ram_c)

rand shr_entry_s shr[1023:0];****
rand rlut_entry_s rlut[1:0];
/** Constraints */

/** Methods */
extern function new(string name = “nvx_aes_shr_ram_c”);
extern function void apply_default_settings();
extern function void randomize_storage();
extern function void print();

endclass: nvx_aes_shr_ram_c

Thanks,
Nainesh

2

In reply to nainesh:

Obviously, there is something you are not showing us as the line you indicate reporting the error is not line 15 of your example.

Are you using packages? If so, where is the typedef in relation to the class definition?

3

In reply to dave_59:

Hi Dave,

typdef shr_entry_s is defined in the package and this package is imported, where I am defining nvx_aes_shr_ram_c class. Error is coming from underlined declaration.

class nvx_aes_shr_ram_c extends uvm_object;
/** UVM Object Utility macro */
`uvm_object_utils(nvx_aes_shr_ram_c)

rand shr_entry_s shr[1023:0];
rand rlut_entry_s rlut[1:0];
/** Constraints */

Thanks,
Nainesh

4

In reply to nainesh:

Try replacing with

rand my_package_name::shr_entry_s shr[1023:0];

where my_package_name is the package you are importing.