Value mismatch after concatenation

SystemVerilog
1

Hi, I am trying to get value from plusarg and concatenate it. I dont see correct value.


bit [5:0]a_cont;
bit [2:0]a;

task get_a();

if (!$value$plusargs("a_value=%d", a)) a = 5;

a_cont = {3'b100,a[2:0]};

`uvm_info("debug", $sformatf("a_cont %h cont %h",a_cont ,{3'b100,a[2:0]}),UVM_LOW);

//after passing value 0 from command line
//following gets printed
// debug : a_cont 00 cont 20

endtask

**Why does a_cont print 00?

2

In reply to UVM_SV_101:

I even tried the arg to be %b

if (!$value$plusargs("a_value=%b", a)) a = 5;

but still a_cont prints 00

3

In reply to UVM_SV_101:

It would help to show a complete example

module top;
  `include "uvm_macros.svh"
  import uvm_pkg::*;

  bit [5:0]a_cont;
  bit [2:0]a;
  task get_a();
     if (!$value$plusargs("a_value=%d", a)) a = 5;
     a_cont = {3'b100,a[2:0]};
     `uvm_info("debug", $sformatf("a_cont %h cont %h",a_cont ,{3'b100,a[2:0]}),UVM_LOW);
  endtask
  initial get_a;
endmodule

This shows the same value for a and a_cont for every simulator on EDAPlayground.