Using $stable as coverpoint expression

SystemVerilog
,
1

Hi All ,
I am testing a scenario where there is No change in value of a variable using $stable as coverpoint expression


bit [2:0]  data ;

 bit clk ;

 always  #5  clk  =  !clk ;
 
 covergroup  cvrgrp  @( posedge  clk );

   coverpoint (  $stable( data , @( posedge  clk ) ) ) // Without clocking event ' @( posedge  clk ) '  I observe Compilation Error 
   {   
       bins  unchanged  =  { 1'b1 } ; 
   }   

 endgroup

 cvrgrp  cvrg1  =  new() ;

 always @( posedge clk )  
   $display(" TIME:%2t  $stable( data )  is %0b " , $time , $stable( data )  );   //  Added  for  debugging

 initial  begin
  
     #4 ; data = 3 ;
    #10 ; data = 3 ;
     #2 ; $finish();

end

I have following 2 questions :

[Q1] Why is it that the clocking event needs to be specified when using $stable in coverpoint expression , whereas within always block it’s inherited

[Q2] In the output at time 15 units , I observe display $stable( data ) is 1
whereas the bin unchanged isn’t covered . Any suggestions why ?

2

In reply to MICRO_91:

[Q1] Why is it that the clocking event needs to be specified when using $stable in coverpoint expression , whereas within always block it’s inherited

Different groups worked on different sections of 1800.
The SVA committee allowed the clocking event in the always to flow through to the assertions and functions like $stable, $past.

That feature was apparently not followed by the committee working on the covergroup.

[Q2] In the output at time 15 units , I observe display $stable( data ) is 1
whereas the bin unchanged isn’t covered . Any suggestions why ?

Tested it, perhaps someone else can answer this.


module m;
 bit [2:0]  data ;
 bit data_stbl;
 bit clk ;
 always  #5  clk  =  !clk ;
 covergroup  cvrgrp  @( posedge  clk );
   coverpoint data_stbl // Without clocking event ' @( posedge  clk ) '  I observe Compilation Error 
   {   
       bins  unchanged  =  { 1'b1 } ; 
   }   
 endgroup
 
 cvrgrp  cvrg1  =  new() ;
 
  always @( posedge clk )  begin 
    data_stbl <= $stable(data); 
   $display(" TIME:%2t  $stable( data )  is %0b " , $time , $stable( data )  );   //  Added  for  debugging
  end
 
 initial  begin
      $dumpfile("dump.vcd"); $dumpvars;
     #4 ; data = 3 ;
    #10 ; data = 3 ;
     #2 ; $finish();
 end
  
 final begin
   $display("COVERAGE:cvrg1.unchanged:%0d", cvrg1.data_stbl.get_coverage());
end
endmodule
/* TIME: 5  $stable( data )  is 0 
 TIME:15  $stable( data )  is 1 
$finish called from file "testbench.sv", line 24.
COVERAGE:cvrg1.unchanged:0
$finish at simulation time                   16 */

Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.

3

Hi,

I believe that the issue is that you do not measure coverage of $stable(data) but of data_stbl signal. And this signal has one clock cycle dalay after $stable(data) caused by the use of nonblocking assignment. This means, that you do not assign imediatelly, but after clocking event. Therefore, you need to simulate at least one more clock cycle.

Jan

4

In reply to galloth:

Good observation, I missed that. I increased the time to #200


TIME:205  $stable( data )  is 1 
# ** Note: $finish    : testbench.sv(24)
#    Time: 214 ns  Iteration: 0  Instance: /m
# COVERAGE:cvrg1.unchanged:100
# End time: 11:12:26 on Feb 26,2023, Elapsed time: 0:00:02