Using auto_bin_max with ignore_bins

SystemVerilog
,
1

I am trying to understand the following code ::


  bit [2:0]  adr1 ;

   covergroup gc ;  //  User  would  Need  to  Call  sample()

      ac : coverpoint adr1
      {
         option.auto_bin_max =  4 ;

         ignore_bins  hi  =  { 6 , 7 }  ;
      }

   endgroup                    

   gc  cg1  =  new() ;

I am confused between the following ::

(1) First the 8 automatic bins are divided into 4 parts . [0:1] , [2:3] , [4:5] and [6:7] and then due to ignore_bins upper range is excluded .

(2) First the ignore_bins comes into picture and the remaining 6 Automatic bins are divided into 4 parts .

I see on tools (1) is used but doesn’t that violate the auto_bin_max = 4 option as (1) has ONLY 3 automatic bins ?

whereas (2) would have 4 automatic bins .

Also if bin hi were declared as illegal_bins , would there be any difference in terms of (1) / (2) ?

2

In reply to hisingh:

Distribution of bins happens before applying ignore/illegal bins. See section 19.5.5 Excluding coverage point values or transitions.

The only difference between ignored and illegal bins is a message.