Using associative arrays with default value in constraint block

SystemVerilog
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1

I wanted some clarification on how associative arrays can be used inside constraint blocks on the rhs side. Specifically associative arrays with “default” index.

According to LRM:

If a default value is specified, then reading a nonexistent element shall yield the specified default value, and
no warning shall be issued

Why then can’t I use such an array inside a constraint block? I get this error when trying to use associative arrays

Error-[CNST-AMME] Constraint array member missing error

Sample code is below:


package my_package;
typedef enum {SMALL, MEDIUM, BIG} size_t;

 bit legal[size_t] = '{SMALL: 0,
                            BIG: 1,
                            default:1};
class Base;
  // Properties
  rand bit test_result;

endclass

endpackage


module GRG_constraint;
  import my_package::*;

  Base  B_h;
  bit result;
  
initial begin
  B_h = new;

  
  result = legal[MEDIUM];		//This is OK
  $display("result = %0d", result);

  if (B_h.randomize() with {test_result == legal[MEDIUM];}) // This is not OK
    $display("test_result = %0d",B_h.test_result);
	else
	  $error("Failed to randomize Base");
    #10;

end

endmodule

I would have assumed the constraint block would pick the default value of legal in the constraint block. If this is not supported, is it expected that all indices of an associative array should be specified?

2

In reply to prang:

It looks like you found a bug in your tool. Please contact your vendor.

3

In reply to prang:

In VCS tool, test_result is not getting the default value, but in other tools, it is getting default value of 1.

4

Thank you for replying. I thought my understanding of associative arrays was wrong!