Unexpected Xs in the result of addition of two logic signals

SystemVerilog
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1

I have a code where two signals are added. Only top bits of the signals are X. Bottom bits are 0s. But the result has all Xs. I would expect the bottom bits to be 0s in the result.


logic [3:0] a; // 4'bxx00
logic [3:0] b; // 4'bxx00
logic [4:0] c;

assign c = a + b; // Results in c = 4'xxxxx

I am trying to understand why the bottom 2 bits are x in the result

2

In reply to AMARDEEP R PALURU:

Because Verilog is pessimistic with arithmetic operators. It implements addition using the host CPU’s arithmetic instructions which only support 2-state addition.