Understanding item.index usage in array reduction method

SystemVerilog
,
1

Hi Forum ,

I have the following Code ::


  class ms_config #( N_MASTER = 2 , N_SLAVE = 3 ) ;

  rand int unsigned txn_map[N_MASTER][N_SLAVE] ;

  rand int unsigned total_txns ;

  rand int unsigned n_txns_per_slave[N_SLAVE] ;

  constraint c_valid { 
                          foreach( n_txns_per_slave[s] )
		n_txns_per_slave[s] == txn_map.sum with ( ( item.index(2) == s ) ? item.sum() : 0 ) ; // [ A ] What does item.index(2) mean ?               
                    }

  constraint MY_VAL {
                          foreach( txn_map[M,N] )
                         txn_map[M][N] inside { [ 1:15] } ;

			 unique { txn_map } ;
		    }


  // constraint TOTAL_TXNS1 {   total_txns == txn_map.sum ; } // [ Q3] 
     constraint TOTAL_TXNS2 {   total_txns == txn_map.sum(item) with ( item.sum(item2) with ( item2 ) ) ; }

  function void post_randomize() ;

         foreach(txn_map[i,j])
        $display("txn_map[%0d][%0d] is %0d",i,j,txn_map[i][j]);

         foreach( n_txns_per_slave[s] )
        $display("n_txns_per_slave[%0d] is %0d",s,n_txns_per_slave[s]);
        
	$display("total_txns is %0d",total_txns );
  endfunction

  endclass

  ms_config#() m ;

  initial begin

    m = new();
    repeat(2)
   if ( m.randomize() )
    begin
      $display("Success ");
    end
  else  
    begin
      $display("Fails ");
    end

  end

[Q1] What does item.index(2) above mean ?

 I understand that   'item' in with() clause would be txn_map[0] and txn_map[1] ( Please correct me if wrong ) 
 Both of them are 1D Unpacked Array 

 **So had I used item.index(1) I would get :: 0 and 1**

[Q2] What does c_valid expression reduce to ?

 Had I used item.index(1) the constraint would reduce to ::


 n_txns_per_slave[0] == ( txn_map[0].sum() + 0 ) ;
 n_txns_per_slave[0] == ( 0 + txn_map[1].sum() ) ;

[Q3] Using Constraint TOTAL_TXNS1 I see following error :: Compilation Error :: “Cannot mix packed and unpacked types in this operation.”

 Using TOTAL_TXNS1 , the resultant expression becomes ::


    total_txns == ( txn_map[0] + txn_map[1] ) ;
    

Is  RHS Operand ( i.e sum of Unpacked Arrays ) even legal ?

Thanks

2

In reply to TC_2017:

Do not use index with any value argument

This is an error in the 1800-2017 LRM. See 0001087: How do array manipulation methods work with multi-D arrays? - Accellera Mantis

Consider that SystemVerilog has arrays of arrays, not multidimensional arrays. That means the first dimension of a 2-d array is actually an unpacked array, which cannot be summed without further reduction.

3

In reply to dave_59:

Hi Dave ,

For the following constraint expression ::


rand bit [2:0] a [10];

  constraint b { foreach (a[i])
    a.sum with (item.index(i) ? int'(item) : 0) == 20;

As you pointed item.index(i) is an error in LRM ,
what is the resultant expression ( via constraint b ) resolved to ?

One of many Output I see is ::

a == {5, 1, 1, 2, 2, 0, 6, 5, 3, 0}

4

In reply to Have_A_Doubt:
Do not use index with any value argument. This is an error in the 1800-2017 LRM.