Understanding force and release

SystemVerilog
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Hi everyone,

Can anyone explain how the force and release commands work with respect to a particular net, port, module input, etc. in a hierarchy?
E.g., If I apply a force command to a lower level block in the hierarchy, will it be forced only from that point in the hierarchy and below, or will the entire net connected to it be forced throughout the entire hierarchy?

I’m looking for an explanation something like this (may not be correct) When forcing a signal, it’s equivalent to disconnecting that signal and connecting a force-driver at that point. The existing signal that was there is disconnected from that point… Releasing it reconnects the original signal and it will be whatever value is currently on the connected signal.

Why am I asking?
I’m asking because when I force and release a reset signal in a lower level fifo block, I’m seeing it affect other things in my design that I’m not expecting (e.g,. other register values are effected. Now I’m not sure I understand what the force/release are doing.

Thank you (again) for sharing with others what what you’ve learned,
Brian

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In reply to BrianK:

A force applies to en entire net. It overrides what ever else is currently driving the net. When you connect a higher level net to a lower net through a port, they are collapsed into a single net that how have two different names. The direction you specified for the port is no longer relevant. The elaboration process essentially flattens out the hierarchy.

Things are different when one or both port connections (higher or lower) is a variable or an expression. In that case the port connection becomes an implicit continuous assignment in the direction specified by the port declaration. The effect of a force can only travel in the same direction as the continuous assignment

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In reply to dave_59:

Hi Dave,

Thanks for the explanation; that makes sense and I had not thought about the case with an expression driving a port.

Brian