Undefined forward class declaration

SystemVerilog
,
1

I have the following code ::


package my_pkg2 ;  // Inside package my_pkg2

import uvm_pkg::* ; // Else Comilation error due to invalid 'uvm_blocking_put_port' type !!

  
  typedef class producer ;  // Class to be declared in top_tb !! . Gives Error although , not sure why
  producer prod ;
  
  class my_blocking_put_port #( type T = int ) extends uvm_blocking_put_port # ( T ) ("put_port" , prod  ) ;
          
  endclass
  
  typedef class consumer ;  // Class to be declared in top_tb !! . Gives Error although , not sure why 
  consumer cons ;
  class my_blocking_put_imp #( type T = int , type IMP = int ) extends uvm_blocking_put_imp # ( T , IMP ) ( "put_imp" , cons ) ;
  
  endclass

endpackage

Now I include and import this my_pkg2.sv in file top_tb.sv



//  Inside file top_tb.sv 
`include "uvm_pkg.sv"
`include "my_pkg2.sv"
`include "uvm_macros.svh" 

import uvm_pkg::*;
import my_pkg2::*;

class producer extends uvm_component ;

 `uvm_component_utils(producer)
  
  // Standard 3 line component constructor here !!
  function void build_phase ( uvm_phase phase ) ;
         prod = this ;
	 put_port = new();
  endfunction


endclass 

class consumer extends uvm_component ;

 `uvm_component_utils(consumer)
  
  // Standard 3 line component constructor here !!

  my_blocking_put_imp #(trans,consumer ) put_imp ;

    function void build_phase ( uvm_phase phase ) ;
	    cons = this ;
	 put_imp = new();
  endfunction


module top_tb ;

.....

endmodule

I get the following error ::
The forward typedef of the class does not have a definition in the same
scope. Please provide a definition to the forward class declaration.

Is typedef limited to same file declaration ?

Any solution to the issue would be appreciated .

Thanks

2

In reply to MICRO_91:

Per the LRM, a forward typedef must be resolved within the same local scope as it is declared. In this case, the scope is considered to be the package ‘my_pkg2’. If the forward typedef was not resolved within the package, then the package becomes dependent on another unknown package, which is not allowed.

3

In reply to MICRO_91:

Forward typedef declarations must be resolved in the scope where they are declared. In your case, you have the typedef inside the package and the class outside. I’m not sure why you want to put the prod/cons variables in the my_pkg2.

Normally one would create an agent or env class component that constructs the producer consumer, and connects the two in its connect phase.

class env extends uvm_env;
function new(string name, uvm_component parent); 
  super.new(nsme,parent); 
endfunction
producer prod;
consumer cons;
function void build_phasse(uvm_phase phase);
 prod = new("prod",this);
 cons = new("cons",this);
endfunction
function void connect_phasse(uvm_phase phase);
  prod.put_port.connect(cons.put_imp);
endfunction
endclass