Transition coverbins

SystemVerilog
, ,
1

Hi, I am trying to cover a scenario using transition bins(using 2 variables) and wanted to know if the code written below works
With the change in the value of either a or b, will the bins get a hit?

bit[1:0] a;
  int b;

  covergroup check@(a or b)
  option.per_instance =1;
  cover_point_a : coverpoint a {
	           bins low = ((2'b00 && (b==32'd10)) => (2'b01 && (b==32'd20)));
                   bins medium = ((2'b00 && (b==32'd10)) => (2'b10 && (b==32'd30)));
                   bins high = ((2'b00 && (b==32'd10)) => (2'b11 && (b==32'd40)));
                   }
2

In reply to Suman Valsange:

You haven’t explained what “works” means, but it most likely does not.

@(a or b) is not a good sampling event, you should be using a clock or an explicit call to sample(). If a and b both change at the same time, there’s no guarantee if you get one or two sample events.

Bins are constructed when the covergroup gets constructed, so the value of b is most likely 0 at that time. so your transition bins get evaluated as 0 => 0, which is not a transition,