Transfer Data from in reg to other reg

SystemVerilog
,
1

Hi,
Let’s us I have defined 2 FIFO as reg as follows,
[65:0] FIFO_1 [1023:0];
[65:0] FIFO_2 [1023:0];

so now let’s say I want to transfer data from FIFO_1 to FIFO_2 if only FIFO_1 location is not zero,

so I am doing like this

for(i=0; i<1024; i++)
if(FIFO_1[i] != 0)
FIFO_2[i] = FIFO_1[i]

so I am facing a problem like if the location 20,40,100 are empty of FIOF_1 then it will also skip that location of FIFO_2 but what I want is that it should write next location data like location 20 is empty then in FIFO_2[20] it should write FIFO_1[21] data.

So What I want that no location of FIFO_2 should be empty.

2

In reply to J_M:
You need another index variable,

for(int i=0,j=0; i<1024; i++)
  if(FIFO_1[i] != 0)
      FIFO_2[j++] = FIFO_1[i]