Is there a way to print the concatenated logic variables RTL path in string format?

SystemVerilog
1

Here is pseudo code of what I am trying to do:

interface test_if();
logic [2:0] merged_enables; 
endinterface

module alignment_check(); 

test_if test_if_inst();

assign test_if_inst.merged_enables = {dut_top.dut.enable1, dut_top.dut.enable2, dut_top.dut.enable3 };

enable_alignment_checker #(2)enable_alignment_checker_check1();

initial begin
enable_alignment_checker_check1.enable_alignment_check(test_if_inst.merged_enables);
end

endmodule

module enable_allignment_checker();

parameter WIDTH = 1;
int i;
logic test_clk = 1'b0;

always #10 test_clk = ~test_clk;

task enable_alignment_check(ref logic [WIDTH:0] merged_clk_enables);
     fork 
       begin
         forever @(test_clk) begin
           for(i=WIDTH; i>0; i--) begin 
             if(merged_clk_enables[i] !== merged_clk_enables[i-1]) begin
               $display("ERROR: ENABLE_ALIGNMENT_CHK_ERROR"); 
             end
           end
         end
       end
     join_none
endtask
endmodule

Could someone help if there is a comparison failure in the task “enable_alignment_check” above, I would like to print the signals in the string format in the display with corresponding RTL paths.

For example, If there is a fail between test_if_inst.merged_enables[0] and test_if_inst.merged_enables[1], I would like to print the corresponding RTL path that is “dut_top.dut.enable2” and “dut_top.dut.enable3”

This will not work I believe, though I haven’t tried:
$display(“ERROR: ENABLE_ALIGNMENT_CHK_ERROR between %s and %s”, merged_clk_enables[i], merged_clk_enables[i-1]);

Please suggest.

2

In reply to prashanth.billava:

There’s no way to do what you want within SystemVerilog language. And even using the VPI C language introspection would be extremely complicated.

Since you are making the hierarchical references and calling the task from the same module alignment_check, you can pass an array of strings representing the paths you want to print to the task.