Is there a standard way to include temperature dependence in systemVerilog?

SystemVerilog
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Hi,

I am trying to model a Power Management block in systemVerilog with real number modeling which has an output with temperature dependence. I think many workarounds can be performed in order to achieve this behavior when simulated in an AMS environment but I was wondering if there is a standard way of doing it?

Thanks,
Mihai

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In reply to mihaiciortuz:

You need to explain more thoroughly what you mean by “temperature dependence”. Are you referring to some sort of delay calculation?