Is there anyway to access .ini file in systemverilog

SystemVerilog
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1

Hi,

I am using .ini file for passing parameter to C-model. I want to pass .ini file to my testbench for parameter parsing. I tried svlib, but couldn’t able to compile it. please provide with one example if there is any such support?

Thanks,
Satya

2

In reply to sathyakiran.p:

Your question is not very clear, but most likely specific to the tool you are using. Please contact your tool vendor directly for support as this forum is not for tool specific help.

3

In reply to sathyakiran.p:

If the format is easy enough, just use $fopen and then parse it in SV.