This is the code, I have written
interface example_inter(input wire clock,reset);
logic [7:0]data_load;
logic [7:0]data_read;
logic rd_en;
logic wr_en;
logic [2:0]count_value;
logic [2:0]count;
task timer(input logic [2:0]count_value, output logic [2:0] count);
forever@(posedge clock)
if(reset)
count <=0;
else
count <= (count < count_value)?(count+1):0;
endtask
modport generator(input data_load, rd_en,wr_en,clock,reset, output data_read);
// modport TB(input data_read,count_value output data_load, rd_en,wr_en,clock,reset,count_out,import task timer());
endinterface
module primary(example_inter.generator example_if);
logic [7:0]data_storage;
always_ff @(posedge example_if.clock) begin
if(example_if.reset)
data_storage <= '0;
else
data_storage <= example_if.data_load;
end
assign example_if.data_read = example_if.rd_en ? data_storage:'0;
endmodule
module testbench(example_inter example);
initial #5
example.timer(example.count_value, example.count);
initial
begin
example.rd_en =1;
example.data_load = 8'b10101111;
example.count_value =5;
#10 $display("out = %b",example.data_read);
end
initial
begin
$dumpfile("dump.vcd"); $dumpvars();
end
endmodule
module top;
logic clock;
logic reset;
initial begin
clock =0;
reset =1;
#6 reset= 0;
end
initial forever #5 clock = ~clock;
example_inter if1(clock, reset);
primary p1(if1);
testbench test(if1);
endmodule