Hi, I have a question regarding vertical bar in systemverilog as in SystemVerilog Book
What does " if(|A) " means in SystemVerilog where A has a type of logic array ?
An example of such syntax is illustrated in Nyuzi
Hi, I have a question regarding vertical bar in systemverilog as in SystemVerilog Book
What does " if(|A) " means in SystemVerilog where A has a type of logic array ?
An example of such syntax is illustrated in Nyuzi
In reply to feiphung:
This is the reduction OR operator. See section 11.4.9 of the IEEE 1800-2012 LRM.