SystemVerilog data types ranges

SystemVerilog
1

Hello everyone,

I don’t know why SystemVerilog 1800-2017 doesn’t talk about the ranges of data types of systemVerilog, Internet doesn’t say much about them too, contrary to software programming languages, once you type “data type range in Software_language_X” in a search engine, you get results immediately. the same applies to vhdl, except that the LRM this times does talk about the range of integer data type, and that the internet also nicely explains the range of the NATURAL and POSITIVE data type too.

Does anyone have an idea where I can find these, for systemverilog ( and why not, vhdl too). or shall I just reason the way these are implemented in C language ( for sv).

Thanks in advance.

2

In reply to Yasmine4:

It’s because we use binary way more than our friends in high-level software. As far as finding the ranges, if a data type contains n bits then its range is


[0, (2 ^ n) - 1]                     // unsigned
[-(2 ^ (n - 1)), (2 ^ (n - 1)) - 1]  // signed two's complement
3

In reply to sbellock:
it makes sense, thank you.