System Verilog constraints in extended class

SystemVerilog
1

Hello,
I am trying to do something as follows

class A 
   int num;
   constraint c_num;
endclass

class B extends A
endclass

class C extends A
endclass

In a separate include file , I would like to add the real constraint for each derived classes

constraint B::c_num
  {  num < 10;}

constraint C::c_num
  {  num > 10;}

I ran into an error , basically it cannot find c_num under B.

What is wrong here ? any other way to achieve this ?

2

Before you can provide an out-of-class body definition for a constraint or method , you must provide an in-class declaration. A constraint requires a null or extern declaration.

class A 
  int num;
  constraint c_num; // optional definition
endclass
 
class B extends A;
  constraint c_num; // optional definition
endclass
 
class C extends A;
  extern constraint c_num; // required definition
endclass

The B::c_num and C::c_num definitions complete the constraints in their respective classes - overriding the A::c_num constraint which happens to be null.

3

In reply to dave_59:

Thanks Dave. This solution works for me…