System Verilog constraints

SystemVerilog
1

I have 10000-bit random variable inside a class. After randomization I want to print sequence like 9,99,999,… so on.

I have tried with below code while calling the display function, value is not printing.

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class a;  
  rand bit [9999:0] abc;
      
    int q1[$] = {0};
    int k1; int k2;
  
function void post_randomize();

    int ab = 9;  
    k1 = q1.pop_back();
    k2 = (k1*10)+ab;
    q1.push_front(k2);
    
   $display("POST_RANDOMIZATION::value=%d",k2);

  endfunction 
  

  constraint c1 {abc == k2;}
  
    function void display();  
      $display("Display value::abc=%d",abc);  
    endfunction
  
endclass 
 



module top;
  initial begin 
    a h1;
    h1 = new();
    
    repeat(10) begin 

      h1.randomize();
      h1.display();
    end
    
  end 
endmodule
2

In reply to sriganeshd:


//It is printing but because of 10000 bits, it have huge initial space due to initial zero values. Use %b if you want to see the effect. 

function void display();
  $display("Display value::abc=%0d",abc);  // use %0d, so it won't print initial space
endfunction
3

In reply to Rahulkumar Patel:

In reply to sriganeshd:


//It is printing but because of 10000 bits, it have huge initial space due to initial zero values. Use %b if you want to see the effect. 
function void display();
$display("Display value::abc=%0d",abc);  // use %0d, so it won't print initial space
endfunction

thank you, Rahulkumar Patel. It worked.

4

In reply to SriGanesh D:

I see one issue in your code.


 constraint c1 {abc == k2;}

abc variable size is 10000 bit but k2 size is 32 bit. so abc will never have value more than (2^32-1) because k2 value limited to (2^32-1)