$ in System Verilog

SystemVerilog
1

What is a $ in System Verilog.

2

In reply to Ravi007:

Sounds like a good interview question. It is used in a number of different constructs.

  • Denote system tasks and PLI routines in identifiers
  • as a separator in specparams
  • as an index for queues
  • as an unbounded range