Hi
Consider we want to model some communication protocol in an interface, using tasks. Such a task will probably contain sequential logic. My question is that is it possible to have a task with sequential logic, in a module/interface which is supposed to be synthesized? I used to think that tasks are synthesizable only if they consume zero simulation time, a condition which makes them very similar to functions. But it just passed my mind that why shouldn’t it be possible to synthesize a task that works with the posedge of the clock, for example? The synthesis tool can easily replace that with regular sequential logic and I don’t see why it should be illegal.
Thanks
In reply to Farhad:
The issue here is not with a task, but having more than one clock cycle in an always process. This is called implicit state machine synthesis. Once that is allowed (and there were some tools that did), then allowing tasks is no longer an issue. Consider
always begin
@(posedge clk) Q <= A;
@(posedge clk) Q <= B;
end
This is an implicit FSM that alternately selects between input A and input B. The problem with this style of coding is synchronizing the implicit FSMs with a reset signal which was very difficult to model in Verilog. It can be done with fork/join statements, but there has not been much demand for it.