Synthesis of Integer

SystemVerilog
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1

Hello,

I understand that it’s not a good idea to use integers in RTL that is to be synthesized. In the following code, it will generate 32 bit incrementor. But my question is on the continuous assignment.

integer I; 
always @(posedge Clock)
  if ( Reset || (I == 255) )
     I <= 0;
  else I <= I + 1;  //32-bit incrementor

  wire [7:0] Count = I;

Will the wire assignment generate an eight bit counter? Or will it simply synthesize into an 8 bit bus.

Thanks.

2

In reply to a72:

If you didn’t have the
(I == 255), which is unnecessary if you only want an 8-bit counter, I would expect synthesis tools to prune dead logic away for logic that does not propagate to any outputs. But the 32-bit equality comparison might interfere with that.

This is probably not the best forum for asking synthesis tool questions. You might try asking here.