Synchronous fifo status flags

SystemVerilog
, ,
1

Hi,

[*] Can anyone suggest me a solution for writing the fifo_empty and fifo_full condition.

I am presently having the status flag as follows,

 assign fifo_empty=((wr_ptr==rd_ptr) ) ? 1:0;
    assign fifo_full=((wr_ptr==5'b11111)&&(rd_ptr==5'b0000))? 1:0;

it can cover for this condition,

  reset=1;
      #10;
      reset=0;
      write=1;
      read=0;
      
      for(int i=0;i<40;i++)
        begin
         #5;
          data_in=i+1;
       #5;
        end
      #5;
      read=1;
      write=0;
   
  ///It can cover the overide condition also.

[*] But the problem with this condition is ,i am not able to cover all the test cases.
for example,this scenario

initial
    clk=0;
  always #5 clk=~clk;
  
  initial
    begin
      
       
      reset=1;
      #10;
      reset=0;

     for(int i=0;i<2;i++) begin
       write = 1;
       read = 0;
       data_in = i+ 1;
       #10;
     end
     for(int i=0;i<2;i++) begin
       write = 0;
       read = 1;
       #10;
     end

     for(int i=0;i<32;i++) begin
      #5;
       write = 1;
      read = 0;
      data_in = i;
      #5;
     end

The ouput is showing my empty flag is asserted,but acc. to standards it need to be low,and full flag needs to be asserted instead.

Thanks & regards,
Veeresh