(SVA) [=N:M] vs [->N:M]

SystemVerilog
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1

Hi All,

What’s the difference between the following assertions:

  1. a[=3:5]
  2. b[->3:5]

It seems in both cases the expressions a and b should happen between 3 and 5 times (not necessary on the consecutive clock cycles).

But what the difference?

Thank you!

2

In reply to dmitryl:

For more understand, I changed your example as:

  1. a ##1 b[=3:5] ##1 c
  2. a ##1 b[->3:5] ##1 c

Case 1: signal c doesn’t have to follow immediately after final b.
Example: a | !b | b | !b | b | !b | b | !b | c

Case 2: signal c has to follow immediately after final b (of course after 1 tick).
Example: a | !b | b | !b | b | !b | b | c