Is in SV code correct for the requirement?

SystemVerilog
1

DUT has data bus of 64 bit which is driven on posedge of clock.
TESTBENCH has data bus of 32 bit which can sample on both posedge and negedge.
On posedge,Drive [0 t0 31] bits of DUT to TB bus and on negedge drive [32 to 63] bits of DUT to TB bus.

Hint given is: All the above logic should be done in the interface itself.

I don’t know how to put all the logic in the interface but the following is my attempt to answer the question. Will it work? Does anyone know the answer to the question?

interface intf(input clk, input reset);
logic[63:0] dut_data;
logic[31:0] tb_data;
  clocking monitor_cb(@clk) 
    input dut_data;
    output tb_data;
  endclocking 
  modport MONITOR(clocking monitor_cb, input clk, input reset);

endinterface

module monitor(intf vif);
task run;
  forever begin
    @(posedge vif.MONITOR.monitor_cb.clk)
    vif.MONITOR.monitor_cb.tb_data[31:0] = vif.MONITOR.monitor_cb.dut_data[31:0];
    @(negedge vif.MONITOR.monitor_cb.clk)
    vif.MONITOR.monitor_cb.tb_data[31:0] = vif.MONITOR.monitor_cb.dut_data[63:32];
  end
endtask
endmodule
2

In reply to Pooja Pathak:

We are not here to do your homework. However, you have no logic in your interface, so you have not answered the question correctly. Using a module is not the solution.

3

In reply to cgales:

It’s not homework. Its a sample interview question from a website. But I did find that always can be used in the interface.

interface intf(input clk, input reset);
  logic[63:0] dut_data;
  logic[31:0] tb_data;
  always@(posedge clk)
    //add valid check here
    tb_data[31:0] = dut_data[31:0];
  always@(negedge clk)
    //add valid check here
    tb_data[31:0] = dut_data[63:32];
    
  clocking monitor_cb(@clk) 
    input dut_data;
    output tb_data;
  endclocking 

  modport MONITOR(clocking monitor_cb, input clk, input reset);
endinterface