Hi all,
While i am making verification plan (systemverilog) to verify one susbsystem module in design i am stuck.
Please help me.
Problem description:
I have a DUT which is encrypted netlist and .sdf file (normally we do functional and timing simulations with these inputs).
From the spec document the DUT contains 16 functional elements(FE’s) and if i want to verify one FE then the following confusions i am having:
1. How to create interface
( where the FE which i am verifying is communication channel which will do all WRITE/READ operations through the processor only and in the DUT there is a master FE which interfaces to all rest of FE’s. Processor all input are connected to that master FE) For simplicity the below is the fig as DUT design:
|---------|-----------------
|Dsp Bus | |Buffer|
|--------- ----------------
| |
| |
---------
|Master FE|
|---------|
| |
| |----|-----------|
--------|COM Channel|
-----------
2. When i am verifying only this comm channel how to take DUT instantiation and signal connections. Since the DUT is having rest 15 FE’s which i am not verifying.
If i am placing this in not correct form please ask me anyother supported queries.
Please help me.
Sreeni.